FPGA Implementation of Viterbi Decoder

Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. The Viterbi algorithm, which is the most extensively employed decoding algorithm for convolutional codes. In this paper, we present a field-programmable gate array implementation of Viterbi Decoder with a constraint length of 11 and a code rate of 1/3. It shows that the larger the constraint length used in a convolutional encoding process, the more powerful the code produced. Key-Words: Convolutional codes, Viterbi Algorithm, Adaptive Viterbi decoder, Path memory, Register Exchange, Field-Programmable Gate Array (FPGA) implementation. Hema S. is M.Tech scholar with the Department of ECE, College of Engineering Trivandrum.E-mail: [email protected] Suresh Babu V. is with the Department of ECE, College of Engineering Trivandrum.E-mail:[email protected] Ramesh P is with the Dept of ECE,,Munnar Engineering. Email : [email protected]